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IS31AP2121 integrated silicon solution, inc. ? www.issi.com 1 rev. 0a, 10/17/2014 2x20w stereo / 1x 40w mono digital audio amplifier with 20 bands eq function s, drc and 2.1ch mode preliminary information october 2014 general description the IS31AP2121 is a digital audio amplifier capable of driving 20w (btl) each to a pair of 8 ? speakers and 40w (pbtl) to a 4 ? speaker operating at 24v supply without external heat-sink or fan. the IS31AP2121 is also capable of driving 4 ? , 10w (se)x2 + 8 ? , 20w (btl)x1 at 24v supply for 2.1ch application. the IS31AP2121 can provide advanced audio processing functions, such as volume control, 20 eq bands, audio mixing, 3d surround sound and dynamic range control (drc). these are fully programmable via a simple i2c control interface. robust protection circuits are provided to protect the IS31AP2121 from damage due to accidental erroneous operating condition. the full digital circuit design of IS31AP2121 is more tolerant to noise and pvt (process, voltage, and temperature) variation than the analog class-ab or class-d audio amplifier counterpart implemented by analog circuit design. IS31AP2121 is pop free during instantaneous power on/off or mute/shut down switching because of its robust built-in anti-pop circuit. applications ? tv audio ? boom-box, cd and dvd re ceiver, docking system ? powered speaker ? wireless audio features ? 16/18/20/24-bits input with i2s, left-alignment and right-alignment data format ? psnr & dr (a-weighting) loudspeaker: 104db (psnr), 110db (dr) @24v ? multiple sampling frequencies (f s ) - 32khz / 44.1khz / 48khz and - 64khz / 88.2khz / 96khz and - 128khz / 176.4khz / 192khz ? system clock = 64x, 128x, 192x, 256x, 384x, 512x, 576x, 768x, 1024x fs - 64x~1024x f s for 32khz / 44.1khz / 48khz - 64x~512x f s for 64khz / 88.2khz / 96khz - 64x~256x f s for 128khz / 176.4khz / 192khz ? supply voltage - 3.3v for digital circuit - 10v~26v for speaker driver ? supports 2.0ch/2.1c h/mono configuration ? loudspeaker output power for at 24v - 10w 2ch into 8 ? @0.16% thd+n for stereo - 15w 2ch into 8 ? @0.19% thd+n for stereo - 20w 2ch into 8 ? @0.25% thd+n for stereo ? sound processing including: - 20 bands parametric speaker eq - volume control (+24db ~ -103db, 0.125db/step), - dynamic range control (drc) - dual band dynamic range control - power clipping - 3d surround sound - channel mixing - noise gate with hysteresis window - bass/treble tone control - bass management crossover filter - dc-blocking high-pass filter ? anti-pop design ? short circuit and over-temperature protection ? supports i2c control without mclk ? i2c control interface with selectable device address ? support bclk system ? support hardware and software reset ? internal pll ? lv under-voltage shutdo wn and hv under-voltage detection ? power saving mode
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 2 rev. 0a, 10/17/2014 typical application circuit figure 1 typical application circuit (for stereo) bead 330pf bead 18 18 330pf outla outlb outra outrb dvdd outla sda IS31AP2121 0.1 f 4.7k v dd outrb dgnd scl 4.7k v dd rstb pdb 1m 1m micro controller 1 f 1 f errorb mclk bclk lrcin sdata vccla vcclb gndl v cc 0.1 f 470 f vccra vccrb gndr v cc 0.1 f 0.1 f 0.1 f outra outlb pbtl 1nf 1nf speaker 4 15 h 6a bead 330pf bead 18 18 330pf 15 h 6a 220nf 100nf 100nf *note 4 *note 4 *note 2 1 23 24 25 19 14 15 21 20 22 36 39 2 3,44 47 48 35 34,41 37 38 46 13,27 9,28 8 digital audio source 470 f figure 2 typical application circuit (for mono) pin logic 0 1 pdb power down normal rstb reset normal pbtl stereo mono
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 3 rev. 0a, 10/17/2014 figure 3 typical application circuit (for 2.1ch) (note 5) pin logic 0 1 pdb power down normal rstb reset normal pbtl x x note 1: when concerning about short-circuit pr otection or performance, it is s uggested using the choke with its i dc larger than 7a. note 2: these capacitors should be plac ed as close to speaker jack as possible, and t heir values should be determined according to emi test results. note 3: the snubber circuit can be removed while the v cc 20v. note 4: when concerning about short-circuit pr otection or performance, it is s uggested using the choke with its i dc larger than 14a. note 5: 2.1ch configuration, it programs by i2c via register address 0x11, d4 bit sem.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 4 rev. 0a, 10/17/2014 pin configuration package pin configuration (top view) elqfp-48 nc 17 18 19 20 21 22 23 24 13 14 15 16 pdb bclk sdata 48 47 46 45 44 43 42 41 40 39 38 37 outlb nc gndl gndl nc scl nc lrcin dvdd sda errorb nc outrb vcclb nc vccrb gndr gndr nc mclk
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 5 rev. 0a, 10/17/2014 pin description no. pin description characteristics 1 outla left channel output a. 2 vccla left channel supply a. 3,44 vcclb left channel supply b. 4~6,10~12 nc not connected. 7 clk_out pll ratio setting pin during power up, this pin is monitored on the rising edge of reset. pmf register will be default set at 1 or 4 times pll ratio. low: pmf [3:0]=[0000], 1 time of pll ratio to avoid system mclk over flow. high: pmf [3:0]=[0100], 4 times of pll ratio. this pin could be clock output pin also during normal operating if en_clk_out register bit is enabled. ttl output buffer, internal pull low with an 80k ? resistor. 8 pbtl stereo/mono configuration pin (low: stereo; high: mono). 9,28 dgnd digital ground. 13,27 dvdd digital power. 14 errorb errorb pin is a dual function pin. one is i2c address setting during power up. the other one is error status report (low active). it sets by register of a_sel_fault at address 0x13 d6 to enable it. this pin is monitored on the rising edge of reset. a value of low (15k ? pull down) sets the i2c device address to 0x30 and a value of high (15k ? pull up) sets it to 0x31. 15 mclk master clock input. schmitt trigger ttl input buffer, internal pull low with an 80k ? resistor. 16~18,26 nc not connected. 19 pdb power down, low active. schmitt trigger ttl input buffer, internal pull high with a 330k ? resistor. 20 lrcin left/right clock input (f s ). schmitt trigger ttl input buffer, internal pull low with an 80k ? resistor. 21 bclk bit clock input (64f s ). schmitt trigger ttl input buffer, internal pull low with an 80k ? resistor. 22 sdata i2s serial audio data input. schmitt trigger ttl input buffer 23 sda i2c serial data. schmitt trigger ttl input buffer 24 scl i2c serial clock input. schmitt trigger ttl input buffer 25 rstb reset, low active. schmitt trigger ttl input buffer, internal pull high with a 330k ? resistor. 29~33,40 nc not connected.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 6 rev. 0a, 10/17/2014 pin description (continue) no. pin description characteristics 34,41 vccrb right channel supply b. 35 vccra right channel supply a. 36 outra right channel output a. 37,38 gndr right channel ground. 39 outrb right channel output b. 42,43,45 nc not connected. 46 outlb left channel output b. 47,48 gndl left channel ground. thermal pad conn ect to dgnd.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 7 rev. 0a, 10/17/2014 ordering information industrial range: 0c to +70c order part no. package qty IS31AP2121-lqls1 e-lqfp-48, lead-free 250/tray copyright ? ? ? 2014 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances ?
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 8 rev. 0a, 10/17/2014 absolute maximum ratings supply for driver stage (vccr, vccl), v cc - 0.3v ~ +30v supply for digital circuit (dvdd), v dd - 0.3v ~ +3.6v input voltage (sda,scl,rstb,pdb,errorb,mclk, bclk,lrcin,sdata,pbtl), v in - 0.3v ~ +3.6v thermal resistance, ja 27.4c/w junction temperature range, t j 0c ~ 150c storage temperature range, t stg - 65c ~ +150c esd (hbm) esd (cdm) tbd note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at t hese or any other condition beyond those i ndicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating condi tions for extended periods may affect device reliability. recommended operating conditions symbol parameter condition min. typ. max. unit v cc supply for driver stage to vccr/l 10 26 v v dd supply for digital circuit 3.15 3.45 v t j junction operating temperature 0 125 c t a ambient operating temperature 0 70 c dc electrical characteristics t a =25c, unless otherwise noted. symbol parameter condition min. typ. max. unit i pdh vcc supply current during power down v cc = 24v 10 200 a i pdl dvdd supply current during power down v dd = 3.3v, pbtl=low 13 20 a i cch quiescent current for vcc (50%/50% pwm duty) v cc = 24v 37 ma i ccl quiescent current for dvdd (un-mute) v dd = 3.3v, pbtl=low 70 ma v uvh under-voltage disabled (for dvdd) 2.8 v v uvl under-voltage enabled (for dvdd) 2.7 v r ds(on) static drain-to-sourc e on-state resistor, pmos v cc =24v, i d = 500ma 260 m ? static drain-to-sourc e on-state resistor, nmos 230 i sc l/r channel over-current protection v cc =24v, i d =500ma (note 1) 7 a mono channel over-current protection 14 t s junction temperature for driver shutdown 158 c temperature hysteresis for recovery from shutdown 33 c
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 9 rev. 0a, 10/17/2014 dc electrical characteristics (continue) t a =25c, unless otherwise noted. symbol parameter condition min. typ. max. unit logic electrical characteristics v ih high level input voltage v dd =3.3v 2.0 v v il low level input voltage v dd =3.3v 0.8 v v oh high level output voltage v dd =3.3v 2.4 v v ol low level output voltage v dd =3.3v 0.4 v c in input capacitance 6.4 pf note 1: loudspeaker over-current protec tion is only effective when loudspeaker drivers ar e properly connected with external lc filters . please refer to the application circuit example for recommended lc filter configuration. ac electrical characteristics t a =25c, v cc =24v, v dd = 3.3v, f s = 48khz, r l =8 ? with passive lc lowpass filter (l= 15h, r dc = 63m ? , c=220nf), input is 1khz sinewave, volu me is 0db unless otherwise specified. symbol parameter condition min. typ. max. unit p o rms output power (note 2) thd+n=0.25%, +8db volume 20 w thd+n=0.19%, +8db volume 15 thd+n=0.16%, +8db volume 10 thd+n total harmonic distortion + noise p o = 7.5w 0.15 % v no output noise 20hz ~ 20 khz (note 3) 120 v snr signal-to-noise ratio +8db volume, input level is -9db (note 3) 104 db dr dynamic range +8db volume, input level is -68db (note 3) 110 db psrr power supply ripple rejection v ripple = 1v rms at 1khz -71 db channel separation 1w @1khz -81 db
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 10 rev. 0a, 10/17/2014 i2c digital input switching characteristics (note 4) symbol parameter standard mode fast mode unit min. max. min. max. f scl serial-clock frequency 0 100 0 400 khz t buf bus free time between a stop and a start condition 4.7 1.3 s t hd, sta hold time (repeated) start condition 4.0 0.6 s t su, sta repeated start condition setup time 4.7 0.6 s t su, sto stop condition setup time 4.0 0.6 s t hd, dat data hold time 0 3.45 0 0.9 s t su, dat data setup time 250 100 ns t low scl clock low period 4.7 1.3 s t high scl clock high period 4.0 0.6 s t r rise time of both sda and scl signals, receiving 1000 20+0.1c b 300 ns t f fall time of both sda and scl signals, receiving 300 20+0.1c b 300 ns c b capacitive load for each bus line 400 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1v dd 0.1v dd v v nh noise margin at the high level for each connected device (including hysteresis) 0.2v dd 0.2v dd v i2s digital input switching characteristics (note 4) symbol parameter condition min. typ. max. unit t lr lrcin period (1/f s ) 10.41 31.25 s t bl bclk rising edge to lrcin edge 50 ns t lb lrcin edge to bclk rising edge 50 ns t bcc bclk period (1/64f s ) 162.76 488.3 ns t bch bclk pulse width high 81.38 244 ns t bcl cblk pulse width low 81.38 244 ns t ds sdata set up time 50 ns t dh sdata hold time 50 ns note 2: thermal dissipation is limited by package type and pcb design. the external heat-sink or system cooling method should be adopt ed for maximum power output. note 3: measured with a-weighting filter. note 4: guaranteed by design.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 11 rev. 0a, 10/17/2014 figure 4 i2c timing figure 5 i2s figure 6 left-alignment figure 7 right-alignment figure 8 system clock timing
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 12 rev. 0a, 10/17/2014 figure 9 timing relationship (using i2s format as an example)
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 13 rev. 0a, 10/17/2014 typical performance characteristics thd+n(%) output power(w) 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 1m 50 5m 10m 50m 100m 500m 1 2 5 10 20 v cc = 24v r l = 8 ? strero 10khz 1khz 20hz figure 10 thd+n vs. output power dbr 20 20k 50 100 200 500 1k 2k 5k 10k frequency(hz) -2 +2 -1.5 1 -0.5 +0 +0.5 +1 +1.5 v cc = 24v r l = 8 ? p o = 1w stereo figure 12 frequency response dbv frequency(h z) 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k 0k -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 +10 +20 v cc = 24v r l = 8 ? stereo figure 14 spectrum at peak snr at -1db signal input frequency(hz) thd+n(%) 20 50 100 200 500 1k 2k 5k 20k 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 r l = 8 ? v cc = 24v strereo p o = 10w p o = 5w p o = 0.5w p o = 1w p o = 0.25w figure 11 thd+n vs. frequency crosstalk(db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency(h z) -120 +0 -100 -80 -60 -40 -20 v cc = 24v r l = 8 ? stereo left to right right to left figure 13 cross-talk dbv frequency(h z) 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k 0k -140 -120 -100 -80 -60 -40 -20 +0 +20 v cc = 24v r l = 8 ? stereo figure 15 spectrum at -60db signal input level
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 14 rev. 0a, 10/17/2014 output power(w) efficiency(%) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 r l = 8 ? stereo v cc =24v v cc =18v v cc =15v v cc =8v v cc =12v figure 16 efficiency vs. output power (power saving mode)
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 15 rev. 0a, 10/17/2014 functional block diagram
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 16 rev. 0a, 10/17/2014 applications information IS31AP2121 has a built-in pll internally, the default volume is muted. IS31AP2121 will activate while the de-mute command via i2c is programmed. operation modes without i2c control the default settings, bass, treble, eq, volume, drc, pll, subwoofer bandwidth, ?, and sub- woofer gain are applied to register table content when using IS31AP2121 without i2c control. the more information about default settings, please refer to the highlighted column of register table section. with i2c control when using i2c control, user can program suitable parameters into IS31AP2121 for their specific applications. please refer to the register table section to get the more detail. internal pll IS31AP2121 has a built-in pll internally. the mclk/f s ratio will be fixed at 1024x, 512x, or 256x with a sample frequency of 48khz, 96khz, or 192khz respectively. a carrier clock frequency is the frequency divided by 128 of master clock. table 1 mclk/f s ratio f s mclk frequency 48khz 49.152mhz 44.1khz 45.158mhz 32khz 32.768mhz reset when the rstb pin is lowered, IS31AP2121 will clear the stored data and reset the register table to default values. IS31AP2121 will exit reset state at the 256 th mclk cycle after the rstb pin is raised to high. power down control IS31AP2121 has a built-in volume fade-in/fade-out design for power down and mute function. the relative power down timing diagrams for loudspeakers are shown below. figure 17 power down timing diagrams with mute figure 18 power down timing diagrams the volume level will be decreased to - db in several lrcin cycles. once the fade-out procedure is finished, IS31AP2121 will turn off the power stages, stop clock signals (mclk, bclk) from feeding into digital circuit and turn off the current of the internal analog circuits. after pdb pin is pulled low, IS31AP2121 needs up to 256 lrcin clocks to finish the above works before entering power down state. users can?t pr ogram IS31AP2121 during power down state, but all the settings of register table will still be kept except that dvdd is removed. if the pd function is disabled in the midway of the fade-out procedure, IS31AP2121 will also execute the fade-in procedure. in addition, IS31AP2121 will establish the analog circuits? bias current and feed the clock signals (mclk, bclk) into digital circuits. then, IS31AP2121 will return to its normal operation without power down. self-protection circuits IS31AP2121 has built-in protection circuits including thermal, short-circuit and under-voltage detection circuits. thermal protection when the internal junction temperature is higher than 158c, power stages will be turned off and IS31AP2121 will return to normal operation once the pdb pdb pdb pdb -103db -103db
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 17 rev. 0a, 10/17/2014 temperature drops to 125c. the temperature values may vary around 10%. short-circuit protection the short-circuit protection circuit protects the output stage when the wires connected to loudspeakers are shorted to each other or gnd/vdd. for normal 24v operations, the current flowing through the power stage will be less than 7a for stereo configuration or less than 14a for mono configuration. otherwise, the short-circuit detectors may pull the errorb pin to dgnd, disabling the output stages. when the over- temperature or short-circuit condition occurs, the open-drain errorb pin will be pulled low and latched into error state. once the over-temperature or short-circuit condition is removed, IS31AP2121 will exit error state when one of the following conditions is met: (1) rstb pin is pulled low. (2) pdb pin is pulled low. (3) master mute is enabled through the i2c interface. under-voltage protection once the v dd voltage is lower than 2.7v, IS31AP2121 will turn off its loudspeaker power stages and cease the operati on of digital processing circuits. when v dd becomes larger than 2.8v, IS31AP2121 will return to normal operation. anti-pop design IS31AP2121 will generate appropriate control signals to suppress pop sounds during initial power on/off, power down/up, mute, and volume level changes. 3d surround sound IS31AP2121 provides the virtual surround sound technology with greater separation and depth voice quality for stereo signals. i2c chip select errorb is an input pin during power. it can be pulled high (15k ? pull up) or low (15k ? pull down). low indicates an i2c address of 0x30, and high an address of 0x31. output configuration the bit 4 [sem] of address 0x11 and pbtl pin defines the configurati on mode. IS31AP2121 can be configured to stereo, mono via pbtl pin (the bit 4 [sem] of address 0x11 default is low). 2.1ch output mode configuration, user can via i2c to program it from the bit 4 [sem] of address 0x11. table 2 provides a reference of available configuration. table 2 output configurations [sem] pbtl configuration mode 0 0 stereo 0 1 mono 1 x 2.1ch figure 19 output configurations
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 18 rev. 0a, 10/17/2014 power on sequence hereunder is IS31AP2121?s power on sequence. give a de-mute command via i2c when the whole system is stable. figure 20 power on sequence table 2 power on sequence symbol condition min. max. unit t1 0 - ms t2 0 - ms t3 10 - ms t4 0 - ms t5 10 - ms t6 10 - ms t7 0 - ms t8 200 - ms t9 20 - ms t10 def=l - 0.1 ms t11 def=h - 0.1 ms t12 25 - ms t13 25 - ms t14 - 22 ms t15 def=l or h - 0.1 ms power off sequence hereunder is IS31AP2121?s power off sequence. vcc vdd mclk bclk lrcin rstb pdb i2c out don?t care t4 t5 t3 t2 t1 figure 21 power off sequence
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 19 rev. 0a, 10/17/2014 table 3 power off sequence symbol min. t1 (with i2c control) 35ms t1 (without i2c control) 5ms t2 0ms (note) t3 0ms t4 1ms t5 1ms note: when t2 is less than 0.1ms, pop noise may occur.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 20 rev. 0a, 10/17/2014 i2c-bus transfer protocol introduction IS31AP2121 employs i2c-bus transfer protocol. two wires, serial data and serial clock carry information between the devices connected to the bus. each device is recognized by a unique 7-bit address and can operate as either a transmitter or a receiver. the master device initiates a data transfer and provides the serial clock on the bus. IS31AP2121 is always an i2c slave device. protocol start and stop condition start is identified by a high to low transition of the sda signal. a start condition must precede any command for data transfer. a stop is identified by a low to high transition of the sda signal. a stop condition terminates communication between IS31AP2121 and the master device on the bus. in both start and stop, the scl is stable in the high state. data validity the sda signal must be stable during the high period of the clock. the high or low change of sda only occurs when scl signal is low. IS31AP2121 samples the sda signal at the rising edge of scl signal. device addressing the master generates 7-bit address to recognize slave devices. when IS31AP2121 receives 7-bit address matched with 0110000 or 0110001 (errorb pin state during power up), IS31AP2121 will acknowledge at the 9th bit (the 8th bit is for r/w bit). the bytes following the device identification address are for IS31AP2121 internal sub-addresses. data transferring each byte of sda signaling must consist of 8 consecutive bits, and the byte is followed by an acknowledge bit. data is transferred with msb first, as shown in the figure below. in both write and read operations, IS31AP2121 suppo rts both single-byte and multi-byte transfers. refer to the figure below for detailed data-transferring protocol. figure 22 data transferring register definitions the IS31AP2121?s audio signal processing data flow is sh own below. users can cont rol these functions by programming appropriate settings in the register table. in this section, the register table is summarized first. the definition of each register follows in the next section.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 21 rev. 0a, 10/17/2014 dual band drc enable (only for stereo mode, pbtl=low) dual bands drc disable i2s m11 m12 m21 m22 prescal prescal asrc asrc eq1 eq2 eq1 eq2 eq7 eq8 eq7 eq8 lch rch l r lrcin bclk sdata pll mclk surround surroun volume drc1 volume drc1 clipping 1 hpfdc postscal 2 fir s/h2 sdm pwm clipping 1 hpfdc postscal 2 fir s/h2 sdm power stage outla outra outrb outlb lch rch i2c scl sda m32 m31 sub eq1 eq2 eq3 eq4 hpf hpf volume drc2 clipping 2 hpfdc postscal 2 fir s/h2 sdm rch lpf
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 22 rev. 0a, 10/17/2014 table 4 register function address name table default 00h state control 1 register 5 000x 0100 01h state control 2 register 6 x000 0100 02h state control 3 register 7 0xxx 1111 03h master volume control register 8 0001 1000 04h~06h channel 1~3 volume register 9 0001 0100 07h,08h bass/treble tone register 10 xxx1 0000 09h bass management crossover frequency r egister 11 xxxx 0010 0ah state control 4 register 12 1001 0000 0bh~0ch channel 1~2 configur ation register 13 xxx1 0010 0dh channel 3 configurat ion register 14 xxx1 0000 0eh drc limiter attack/release rate register 15 0110 1010 0fh~10h reserved - - 11h state control 5 register 16 xx11 0010 12h vcc under-volt age selection register 17 1xxx 0001 13h noise gate gain register 18 x000 xx00 14h coefficient ram base ad dress register 19 x000 0000 15h~23h user-defined coeffi cients register 20~24 - 24h coefficients control register 25 xxxx 0000 25h~29h reserved - - 2ah power saving mode switching level register 26 xxx0 1101 2bh volume fine tune register 27 0011 1111 note: the reserved registers are not allowed to writ e any bits in them, or the ic will be abnormal. table 5 00h state control 1 register bit d7:d5 d4 d3 name if - pwml_x default 000 x 0 bit d2 d1 d0 name pwmr_x lv_uvsel lrexc default 1 0 0 IS31AP2121 supports multiple serial data input formats including i2s, left-alignment and right- alignment. these formats are selected by users via d7~d5 of addre ss 00h. the left/r ight channels can be exchanged to each other by programming to address 00h/d0, lrexc. if input format 000 i2s 16-24 bits 001 left-alignment 16-24 bits 010 right-alignment 16 bits 011 right-alignment 18 bits 100 right-alignment 20 bits 101 right-alignment 24 bits others not available pwml_x outla/b exchange 0 no exchanged 1 l/r exchanged pwmr_x outra/b exchange 0 l/r exchanged 1 no exchanged
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 23 rev. 0a, 10/17/2014 lv_uvsel lv under-voltage selection 0 2.7v 1 3.0v lrexc left/right ch annel exchanged 0 no exchange 1 l/r exchange table 6 01h state control 2 register bit d7: d6 d5:d4 d3:d0 name - bclk_sel fs pmf default x 0 00 0100 IS31AP2121 has a built-in pll and multiple mclk/fs ratios are supported. detail setting is shown in the following table. bclk_sel mclk-less (bclk system) 0 disabled 1 enable fs sampling frequency 00 32/44.1/48khz 01 64/88.2/96khz 1x 128/176.4/192khz pmf multiple mclk/f s ratio setting 0000 1024x(fs=00)/ 512x(fs=01)/ 256x(fs=1x) 0001 64x 0010 128x 0011 192x 0100 256x 0101 384x (not available when fs=1x) 0110 512x (not available when fs=1x) 0111 576x (not available when fs=01,1x) 1000 768x (not available when fs=01,1x) 1001 1024x (not available when fs=01,1x) others not available note: the fs pmf should be lower than 49.152mhz, or the system will be error. table 7 02h state control 3 register bit d7 d6:d4 d3 d2:d0 name en_clk_out - mute cm1:cm3 default 0 xxx 1 111 IS31AP2121 has mute function including master mute and channel mute. when master mute is enabled, all 3 processing channels are muted. user can mute these 3 channels individually by channel mute. when the mute function is enabled or disabled, the fade-out or fade-in process will be initiated. en_clk_out pll clock output 0 disabled 1 enable mute master mute 0 all channel not muted 1 all channel muted cmx channel x mute 0 channel x not muted 1 only channel x muted table 8 03h master volume control register bit d7:d0 name mv default 0001 1000 IS31AP2121 supports both master-volume (03h register) and channel-volume control (04h, 05h and 06h registers) modes. both volume control settings range from +12db ~ -103db and 0.5db per step. note that the master volume control is added to the individual channel volume control as the total volume control. for example, if the master volume level is set at, level a (in db unit) and the channel volume level is set at level b (in db unit), the total volume control setting is equal to level a plus with level b. -103db total volume (level a + level b) +24db. mv master volume 0000 0000 +12.0db 0000 0001 +11.5db 0000 0010 +11.0db ? 0001 1000 0db ? 1110 0110 -103.0db 1110 0111 - others -
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 24 rev. 0a, 10/17/2014 table 9 04h~06h channel 1~3 volume registers bit d7:d0 name cxv default 0001 0100 cxv channel x volume 0000 0000 +12.0db 0000 0001 +11.5db ? 0001 0100 +2db ? 1110 0110 -103.0db 1110 0111 - others - table 10 07h/08h bass/treble tone registers bit d7:d5 d6:d0 name - btc/ttc default xxx 10000 last two sets of eq can be programmed as bass/treble tone boost and cut. when, 0ah register, d6, bte is set to high, the eq-7 and eq-8 will perform as bass and treble respectively. the -3db corner frequency of bass is 360hz, and treble is 7khz. the gain range for both filters is +12db ~ - 12db with 1db per step. btc/ttc bass/treble gain setting 00000 +12db ? 00100 +12db 00101 +11db ? 10000 0db 10001 -1db ? 111xx -12db table 11 09h bass management crossover frequency register bit d7:d4 d3:d0 name - xo default xxxx 0010 the IS31AP2121 provides bass management crossover frequency selection. a 1 st order high-pass filter (channel 1 and 2) and a 2 nd order low-pass filter (channel 3) at selected frequency are performed. xo bass management crossover frequency 0000 80hz 0001 100hz 0010 120hz 0011 140hz 0100 160hz 0101 180hz 0110 200hz 0111 300hz 1000 400hz 1001 500hz 1010 600hz 1011 700hz 1100 800hz 1101 900hz 1110 1000hz 1111 reserved table 12 0ah state control 4 register bit d7 d6 d5 d4 name srbp bte tbdrce nge default 1 0 0 1 bit d3 d2 d1 d0 name eql psl dspb hpb default 0 0 0 0 the IS31AP2121 provides several dsp setting as following. srbp surround bypass 0 surround enable 1 surround bypass bte bass/treble selection bypass 0 bass/treble disable 1 bass/treble enable tbdrce two band drc enable 0 two band drc disable 1 two band drc enable nge noise gate enable 0 noise gate disable 1 noise gate enable eql eq link 0 each channel uses individual eq 1 channel-2 uses channel-1 eq psl post-scale link 0 each channel uses individual post-scale 1 use channel-1 post-scale
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 25 rev. 0a, 10/17/2014 dspb eq bypass 0 eq enable 1 eq bypass hpb dc blocking hpf bypass 0 hpf dc enable 1 hpf dc bypass table 13 0bh~0ch channel 1~2 configuration registers bit d7:d5 d4 d3 name - cxdrcm cxpcbp default xxx 1 0 bit d2 d1 d0 name cxdrcbp cxhpfbp cxvbp default 0 1 0 the IS31AP2121 can configure each channel to enable or bypass drc and channel volume and select the limiter set. IS31AP2121 support two mode of drc, rms and peak detection which can be selected via d4. cxdrcm channel 1/2 drc mode 0 peak detection 1 rms detection cxpcbp channel 1/2 power clipping bypass 0 channel 1/2 pc enable 1 channel 1/2 pc bypass cxdrcbp channel 1/2 drc bypass 0 channel 1/2 drc enable 1 channel 1/2 drc bypass cxhpfbp channel 1/2 bass management hpf bypass 0 channel 1/2 hpf enable 1 channel 1/2 hpf bypass cxvbp channel 1/2 volume bypass 0 channel 1/2?s master volume operation 1 channel 1/2?s master volume bypass table 14 0dh channel 3 configuration register bit d7:d5 d4 d3 name - c3drcm c3pcbp default xxx 1 0 bit d2 d1 d0 name c3drcbp c3hpfbp c3vbp default 0 0 0 the IS31AP2121 can configure each channel to enable or bypass drc and channel volume and select the limiter set. IS31AP2121 support two mode of drc, rms and peak detection which can be selected via d4. c3drcm channel 3 drc mode 0 peak detection 1 rms detection c3pcbp channel 3 power clipping bypass 0 channel 3 pc enable 1 channel 3 pc bypass c3drcbp channel 3 drc bypass 0 channel 3 drc enable 1 channel 3 drc bypass c3hpfbp channel 3 bass management lpf bypass 0 channel 3 lpf enable 1 channel 3 lpf bypass c3vbp channel 3 volume bypass 0 channel 3 volume operation 1 channel 3 volume bypass table 15 0eh drc limiter attack/release rate register bit d7:d5 d6:d0 name la lr default 0110 1010 the IS31AP2121 defines a set of limiter. the attack/release rates are defines as following table. la drc attack rate 0000 3db/ms 0001 2.667db/ms 0010 2.182db/ms 0011 1.846db/ms 0100 1.333db/ms 0101 0.889db/ms
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 26 rev. 0a, 10/17/2014 0110 0.4528db/ms 0111 0.2264db/ms 1000 0.15db/ms 1001 0.1121db/ms 1010 0.0902db/ms 1011 0.0752db/ms 1100 0.0645db/ms 1101 0.0563db/ms 1110 0.0501db/ms 1111 0.0451db/ms lr drc release rate 0000 0.5106db/ms 0001 0.1371db/ms 0010 0.0743db/ms 0011 0.0499db/ms 0100 0.0360db/ms 0101 0.0299db/ms 0110 0.0264db/ms 0111 0.0208db/ms 1000 0.0198db/ms 1001 0.0172db/ms 1010 0.0147db/ms 1011 0.0137db/ms 1100 0.0134db/ms 1101 0.0117db/ms 1110 0.0112db/ms 1111 0.0104db/ms table 16 11h state control 5 register bit d7:d6 d5 d4 d3 name - sw_rstb lvuv_fade sem default xx 1 1 0 bit d2 d1 d0 name dis_mclk_det qt_en pwm_sel default 0 1 0 sw_rstb software reset 0 reset 1 normal operation lvuv_fade low under-voltage fade 0 no fade 1 fade sem single end mode 0 2.0 mode (2btl or 1pbtl) 1 2.1 mode (2se+1btl) dis_mclk_det disable mclk detect circuit 0 enable mclk detect circuit 1 disable mclk detect circuit qt_en power saving mode 0 disable 1 enable pwm_sel pwm modulation 0 qua-ternary 1 ternary table 17 12h vcc under-voltage selection register bit d7 d6:d4 d3:d0 name dis_hvuv - hv_uvsel default 1 xxx 0001 IS31AP2121 can disable hv under-voltage detection via d7. IS31AP2121 support multi-level hv under- voltage detection via d3~ d0, using this function, IS31AP2121 will fade out signal to avoid pop sounds if high voltage supply disappear before low voltage supply. dis_hvuv disable hv under-voltage selection 0 enable 1 disable hv_uvsel uv detection level 0000 8.2v 0001 9.7v 0011 13.2v 0100 15.5v 1100 19.5v others 9.7v table 18 13h noise gate gain register bit d7 d6 d5 name - a_sel_fault d_mod default x 0 0 bit d4 d3:d2 d1:d0 name dis_ng_fade - ng_gain default 0 xx 00 the errorb pin of IS31AP2121 is a dual function pin. it is treated as an i2c device address selection input when d6 is set as low. it will become as an error output pin when d6 is set as high. IS31AP2121 provide noise gate function if receiving 2048 signal sample points smaller than noise gate attack level. user can change noise gate gain via
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 27 rev. 0a, 10/17/2014 d1~ d0. when noise gate function occurs, input signal will multiply noise ga te gain (x1/8, x1/4 x1/2, x0). user can select fade out or not via d4. a_sel_fault i2c address selection or error output 0 i2c address selection 1 error output d_mod delta quaternary modulation 0 disable 1 enable dis_ng_fade disable noise gate fade 0 fade 1 no fade ng_gain noise gate gain 00 x1/8 01 x1/4 10 x1/2 11 mute table 19 14h coefficient ram base address register bit d7 d6:d0 name - cfa default x 000 0000 an on-chip ram in IS31AP2121 stores user-defined eq and mixing coefficients. the content of this coefficient ram is indirectly accessed via coefficient registers, which consist of one base address register (14h), five sets of registers (15h ~ 23h) of three consecutive 8-bit entries for each 24-bit coefficient, and one control register (24h) to control access of the coefficients in the ram. cfa coefficient ram base address table 20 15h~17h user-defined coefficients registers (top/middle/bottom 8-bits of coefficients a1) bit d7:d0 name c1b default - table 21 18h~1ah user-defined coefficients registers (top/middle/bottom 8-bits of coefficients a2) bit d7:d0 name c2b default - table 22 1bh~1dh user-defined coefficients registers (top/middle/bottom 8-bits of coefficients a1) bit d7:d0 name c3b default - table 23 1eh~20h user-defined coefficients registers (top/middle/bottom 8-bits of coefficients b2) bit d7:d0 name c4b default - table 24 21h~23h user-defined coefficients registers (top/middle/bottom 8-bits of coefficients a0) bit d7:d0 name c5b default - table 25 24h coefficients control register bit d7:d4 d3 d2 d1 d0 name - ra r1 wa w1 default xxxx 0 0 0 0 ra enable of reading a set of coefficients from ram 0 read complete 1 read enable r1 enable of reading a single coefficient from ram 0 read complete 1 read enable wa enable of writing a set of coefficients to ram 0 write complete 1 write enable w1 enable of writing a single coefficient to ram 0 write complete 1 write enable
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 28 rev. 0a, 10/17/2014 table 26 2ah power saving mode switching level register bit d7:d5 d4:d0 name qt_sw_window qt_sw_level default 000 01101 if the pwm exceeds the programmed switching power level (default 26 40ns), the modulation algorithm will change from quaternary into power saving mode. it results in higher power efficiency during larger power output operations. if the pwm drops below the programmed switching power level - power saving mode hysteresis window, the modulation algorithm will change back to quaternary modulation. qt_sw_window power saving mode hysteresis window 000 2 001 3 010 4 011 5 100 6 101 7 110 8 111 9 qt_sw_level switching level 00000 4 00001 4 ? 01101 26 01110 28 01111 30 ? 11110 60 11111 62 table 27 2bh volume fine tune register bit d7:d6 d5:d4 d3:d2 d1:d0 name mv_ft c1v_ft c2v_ft c3v_ft default 00 11 11 11 IS31AP2121 supports both master-volume fine tune and channel-volume control fine tune modes. both volume control settings range from 0db ~ -0.375db and 0.125db per step. note that the master volume fine tune is added to the individual channel volume fine tune as the total volume fine tune. mv_ft master volume fine tune 00 0db 01 -0.125db 10 -0.25db 11 -0.375db c1v_ft channel 1 volume fine tune 00 0db 01 -0.125db 10 -0.25db 11 -0.375db c2v_ft channel 2 volume fine tune 00 0db 01 -0.125db 10 -0.25db 11 -0.375db c3v_ft channel 3 volume fine tune 00 0db 01 -0.125db 10 -0.25db 11 -0.375db ram access the procedure to read/write coefficient(s) from/to ram is as followings: read a single coefficient from ram: 1. write 7-bits of address to i2c address-0x14 2. write 1 to r1 bit in address-0x24 3. read top 8-bits of coefficient in i2c address-0x15 4. read middle 8-bits of coefficient in i2c address- 0x16 5. read bottom 8-bits of coefficient in i2c address- 0x17 read a set of coefficients from ram: 1. write 7-bits of address to i2c address-0x14 2. write 1 to ra bit in address-0x24 3. read top 8-bits of coefficient a1 in i2c address- 0x15 4. read middle 8-bits of coefficient a1in i2c address-0x16 5. read bottom 8-bits of coefficient a1 in i2c address-0x17 6. read top 8-bits of coefficient a2 in i2c address- 0x18 7. read middle 8-bits of coefficient a2 in i2c address-0x19 8. read bottom 8-bits of coefficient a2 in i2c address-0x1a 9. read top 8-bits of coefficient b1 in i2c address- 0x1b
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 29 rev. 0a, 10/17/2014 10. read middle 8-bits of coefficient b1 in i2c address-0x1c 11. read bottom 8-bits of coefficient b1 in i2c address-0x1d 12. read top 8-bits of coefficient b2 in i2c address- 0x1e 13. read middle 8-bits of coefficient b2 in i2c address-0x1f 14. read bottom 8-bits of coefficient b2 in i2c address-0x20 15. read top 8-bits of coefficient a0 in i2c address- 0x21 16. read middle 8-bits of coefficient a0 in i2c address-0x22 17. read bottom 8-bits of coefficient a0 in i2c address-0x23 write a single coefficient from ram: 1. write 7-bis of address to i2c address-0x14 2. write top 8-bits of coefficient in i2c address-0x15 3. write middle 8-bits of coefficient in i2c address- 0x16 4. write bottom 8-bits of coefficient in i2c address- 0x17 5. write 1 to w1 bit in address-0x24 write a set of coefficients from ram: 1. write 7-bits of address to i2c address-0x14 2. write top 8-bits of coefficient a1 in i2c address- 0x15 3. write middle 8-bits of coefficient a1 in i2c address-0x16 4. write bottom 8-bits of coefficient a1 in i2c address-0x17 5. write top 8-bits of coefficient a2 in i2c address- 0x18 6. write middle 8-bits of coefficient a2 in i2c address-0x19 7. write bottom 8-bits of coefficient a2 in i2c address-0x1a 8. write top 8-bits of coefficient b1 in i2c address- 0x1b 9. write middle 8-bits of coefficient b1 in i2c address-0x1c 10. write bottom 8-bits of coefficient b1 in i2c address-0x1d 11. write top 8-bits of coefficient b2 in i2c address- 0x1e 12. write middle 8-bits of coefficient b2 in i2c address-0x1f 13. write bottom 8-bits of coefficient b2 in i2c address-0x20 14. write top 8-bits of coefficient a0 in i2c address- 0x21 15. write middle 8-bits of coefficient a0 in i2c address-0x22 16. write bottom 8-bits of coefficient a0 in i2c address-0x23 17. write 1 to wa bit in address-0x24 note: the read and write operation on ram coefficients works only if lrcin (pin 15) switching on rising edge. and, before each writing operation, it is necessary to read the address-0x24 to confirm whether ram is writable current in first. if the logic of w1 or wa is high, the coefficient writing is prohibited. user-defined equalizer the IS31AP2121 provides 20 parametric equalizer (eq). users can program suitable coefficients via i2c control interface to program the required audio band frequency response for every eq. the transfer function 2 2 1 1 2 2 1 1 0 ) ( 1 ? ? ? ? ? ? ? ? ? z b z b z a z a a h z the data format of 2?s complement binary code for eq coefficient is 3.21. i.e., 4-bits for integer (msb is the sign bit) and 21-bits for mantissa. each coefficient range is from 0x800000 (-4) to 0x7fffff (+3.999999523). these coefficients are stored in user defined ram and are referenced in following manner: chxeqya0=a0 chxeqya1=a1 chxeqya2=a2 chxeqyb1=-b1 chxeqyb2=-b2 where x and y represents the number of channel and the band number of eq equalizer. all user-defined filters are path-through, where all coefficients are defaulted to 0 after being powered up, except the a0 that is set to 0x200000 which represents 1. mixer the IS31AP2121 provides mixers to generate the extra audio source from the input left and right channels. the coefficients of mixers are defined in range from 0x800000 (-1) to 0x7fffff (0.9999998808). the function block diagram is as following figure:
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 30 rev. 0a, 10/17/2014 figure 23 mixer function block diagram pre-scale for each audio channel, IS31AP2121 can scale input signal level prior to eq processing which is realized by a 24-bit signed fractional multiplier. the pre-scale factor, ranging from -1 (0x800000) to 0.9999998808 (0x7fffff), for this multiplier, can be loaded into ram. the default values of the pre- scaling factors are set to 0x7fffff. programming of ram is described in ram access. post-scale the IS31AP2121 provides an additional multiplication after equalizing and before interpolation stage, which is realized by a 24-bit signed fractional multiplier. the post-scaling factor, ranging from -1 (0x800000) to 0.9999998808 (0x7fffff), for this multiplier, can be loaded into ram. the default values of the post-scaling factors are set to 0x7fffff. all channels can use the channel-1 post-scale factor by setting the post-scale link. programming of ram is described in ram access. power clipping the IS31AP2121 provides power clipping function to avoid excessive signal that may destroy loud speaker. two sets of power clipping are provided. one is used for both channel 1 and channel 2, while the other is used for channel 3. the power clipping level is defined by 24-bit representation and is stored in ram address 0x6f and 0x70. the following table shows the power clipping level?s numerical representation. table 28 sample calculation for power clipping max. amplitude db linear decimal hex (3.21 format) v cc 0 1 2097152 200000 v cc 0.707 -3 0.707 1482686 169fbe v cc 0.5 -6 0.5 1048576 100000 v cc l x l= 10 (x/20) d= 2097152 l h= dec2hex(d) attack threshold the IS31AP2121 provides power limited function. when the input rms exceeds the programmable attack threshold value, the output power will be limited by this threshold power level via gradual gain reduction. two sets of power limit are provided. one is used of channel 1 and channel 2, while the other is used for channel 3. attack threshold is defined by 24-bit representation and is stored in ram address 0x71 and 0x72. release threshold after IS31AP2121 has reached the attack threshold, its output power will be limited to that level. the output power level will be gr adually adjusted to the programmable release threshold level. two sets of power limit are provided. one is used of channel 1 and channel 2, while the other is used for channel 3. release threshold is defined by 24-bit representation and is stored in ram address 0x73 and 0x74. the following table shows the attack and release threshold?s numerical representation. table 29 sample calculation for attack and release threshold power db linear decimal hex (3.21 format) (v cc ^ 2)/r 0 1 2097152 200000 (v cc ^ 2)/2r -3 0.5 1048576 100000 (v cc ^ 2)/4r -6 0.25 524288 80000 (v cc ^ 2)/r l x l= 10 (x/10) d= 2097152 l h= dec2hex(d) to best illustrate the power limit function, please refer to the following figure.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 31 rev. 0a, 10/17/2014 input attack threshold attack threshold release threshold release threshold output attack threshold attack threshold release threshold release threshold gain attack rate= ? gain1/ ? t1 release rate= ? gain2/ ? t2 ? t1 ? t2 ? gain1 ? gain2 touch attack threshold under release threshold figure 24 attack and release threshold noise gate attack level when both left and right signals have 2048 consecutive sample points less than the programmable noise gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8, x1/4, x1/2, or zero if the noise gate function is enabled. noise gate attack level is defined by 24- bit representation and is stored in ram address 0x75. noise gate release level after entering the noise gating status, the noise gain will be removed whenever IS31AP2121 receives any input signal that is more than the noise gate release level. noise gate release level is defined by 24-bit representation and is stored in ram address 0x76. the following table shows the noise gate attack and release threshold level?s numerical representation. table 30 sample calculation for noise gate attack and release level input amplitude linear decimal hex (1.23 format) 0db 1 8388607 7fffff -100db 10 -5 83 53 -110db 10 -5.5 26 1a xdb l= 10 (x/20) d= 8388607 l h= dec2hex(d) drc energy coefficient figure 25 digital processing of calculating rms signal power the above figure illustrates the digital processing of calculating rms signal power. in this processing, a drc energy coefficient is required, which can be programmed for different frequency range. two sets of energy coefficients are provided. one is used of channel 1 and channel 2, while the other is used for channel3. energy coefficient is defined by 24-bit representation and is stored in ram address 0x77 and 0x78. the following table shows the drc energy coefficient numerical representation.
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 32 rev. 0a, 10/17/2014 table 31 sample calculation for drc energy coefficient drc energy coefficient db linear decimal hex (1.23 format) 1 0 1 8388607 7fffff 1/256 -48.2 1/256 32768 8000 1/1024 -60.2 1/1024 8192 2000 l x l= 10 (x/20) d= 8388607 l h= dec2hex(d)
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 33 rev. 0a, 10/17/2014 the user defined ram the contents of user defined ram is represented in following table. table 32 user defined ram address name coefficient default address name coefficient default 0x00 channel 1 eq1 ch1eq1a1 0x000000 0x32 channel 2 eq1 ch2eq1a1 0x000000 0x01 ch1eq1a2 0x000000 0x33 ch2eq1a2 0x000000 0x02 ch1eq1b1 0x000000 0x34 ch2eq1b1 0x000000 0x03 ch1eq1b2 0x000000 0x35 ch2eq1b2 0x000000 0x04 ch1eq1a0 0x200000 0x36 ch2eq1a0 0x200000 0x05 channel 1 eq2 ch1eq2a1 0x000000 0x37 channel 2 eq2 ch2eq2a1 0x000000 0x06 ch1eq2a2 0x000000 0x38 ch2eq2a2 0x000000 0x07 ch1eq2b1 0x000000 0x39 ch2eq2b1 0x000000 0x08 ch1eq2b2 0x000000 0x3a ch2eq2b2 0x000000 0x09 ch1eq2a0 0x200000 0x3b ch2eq2a0 0x200000 0x0a channel 1 eq3 ch1eq3a1 0x000000 0x3c channel 2 eq3 ch2eq3a1 0x000000 0x0b ch1eq3a2 0x000000 0x3d ch2eq3a2 0x000000 0x0c ch1eq3b1 0x000000 0x3e ch2eq3b1 0x000000 0x0d ch1eq3b2 0x000000 0x3f ch2eq3b2 0x000000 0x0e ch1eq3a0 0x200000 0x40 ch2eq3a0 0x200000 0x0f channel 1 eq4 ch1eq4a1 0x000000 0x41 channel 2 eq4 ch2eq4a1 0x000000 0x10 ch1eq4a2 0x000000 0x42 ch2eq4a2 0x000000 0x11 ch1eq4b1 0x000000 0x43 ch2eq4b1 0x000000 0x12 ch1eq4b2 0x000000 0x44 ch2eq4b2 0x000000 0x13 ch1eq4a0 0x200000 0x45 ch2eq4a0 0x200000 0x14 channel 1 eq5 ch1eq5a1 0x000000 0x46 channel 2 eq5 ch2eq5a1 0x000000 0x15 ch1eq5a2 0x000000 0x47 ch2eq5a2 0x000000 0x16 ch1eq5b1 0x000000 0x48 ch2eq5b1 0x000000 0x17 ch1eq5b2 0x000000 0x49 ch2eq5b2 0x000000 0x18 ch1eq5a0 0x200000 0x4a ch2eq5a0 0x200000 0x19 channel 1 eq6 ch1eq6a1 0x000000 0x4b channel 2 eq6 ch2eq6a1 0x000000 0x1a ch1eq6a2 0x000000 0x4c ch2eq6a2 0x000000 0x1b ch1eq6b1 0x000000 0x4d ch2eq6b1 0x000000 0x1c ch1eq6b2 0x000000 0x4e ch2eq6b2 0x000000 0x1d ch1eq6a0 0x200000 0x4f ch2eq6a0 0x200000
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 34 rev. 0a, 10/17/2014 table 32 user defined ram (continues) address name coefficient default address name coefficient default 0x1e channel 1 eq7 ch1eq7a1 0x000000 0x50 channel 2 eq7 ch2eq7a1 0x000000 0x1f ch1eq7a2 0x000000 0x51 ch2eq7a2 0x000000 0x20 ch1eq7b1 0x000000 0x52 ch2eq7b1 0x000000 0x21 ch1eq7b2 0x000000 0x53 ch2eq7b2 0x000000 0x22 ch1eq7a0 0x200000 0x54 ch2eq7a0 0x200000 0x23 channel 1 eq8 ch1eq8a1 0x000000 0x55 channel 2 eq8 ch2eq8a1 0x000000 0x24 ch1eq8a2 0x000000 0x56 ch2eq8a2 0x000000 0x25 ch1eq8b1 0x000000 0x57 ch2eq8b1 0x000000 0x26 ch1eq8b2 0x000000 0x58 ch2eq8b2 0x000000 0x27 ch1eq8a0 0x200000 0x59 ch2eq8a0 0x200000 0x28 channel 3 eq1 ch1eq9a1 0x000000 0x5a channel 3 eq2 ch2eq9a1 0x000000 0x29 ch1eq9a2 0x000000 0x5b ch2eq9a2 0x000000 0x2a ch1eq9b1 0x000000 0x5c ch2eq9b1 0x000000 0x2b ch1eq9b2 0x000000 0x5d ch2eq9b2 0x000000 0x2c ch1eq9a0 0x200000 0x5e ch2eq9a0 0x200000 0x2d channel 3 eq3 ch3eq1a1 0x000000 0x5f channel 3 eq4 ch3eq2a1 0x000000 0x2e ch3eq1a2 0x000000 0x60 ch3eq2a2 0x000000 0x2f ch3eq1b1 0x000000 0x61 ch3eq2b1 0x000000 0x30 ch3eq1b2 0x000000 0x62 ch3eq2b2 0x000000 0x31 ch3eq1a0 0x200000 0x63 ch3eq2a0 0x200000
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 35 rev. 0a, 10/17/2014 table 32 user defined ram (continues) address name coefficient default 0x64 channel 1 mixer1 m11 0x7fffff 0x65 channel 1 mixer2 m12 0x000000 0x66 channel 2 mixer1 m21 0x000000 0x67 channel 2 mixer2 m22 0x7fffff 0x68 channel 3 mixer1 m31 0x400000 0x69 channel 3 mixer2 m32 0x400000 0x6a channel 1 prescale c1prs 0x7fffff 0x6b channel 2 prescale c2prs 0x7fffff 0x6c channel 1 postscale c1pos 0x7fffff 0x6d channel 2 postscale c2pos 0x7fffff 0x6e channel 3 postscale c3pos 0x7fffff 0x6f ch1.2 power clipping pc1 0x200000 0x70 ch3 power clipping pc2 0x200000 0x71 ch1.2 drc attack thre shold drc1_ath 0x200000 0x72 ch1.2 drc release th reshold drc1_rth 0x80000 0x73 ch3 drc attack thre shold drc2_ath 0x200000 0x74 ch3 drc release th reshold drc2_rth 0x80000 0x75 noise gate attack level ngal 0x0001a 0x76 noise gate release level ngrl 0x000053 0x77 drc1 energy coefficient drc1_ec 0x8000 0x78 drc2 energy coefficient drc2_ec 0x2000
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 36 rev. 0a, 10/17/2014 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 26 classification profile
IS31AP2121 integrated silicon solution, inc. ? www.issi.com 37 rev. 0a, 10/17/2014 package information elqfp-48

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